Apparatus for detecting abnormal conditions of transmitted signals

ABSTRACT

In a protective relaying system wherein a carrier wave frequency modulated by an electric quantity is transmitted to a receiving station for operating a relay and an abnormal condition of the transmitted signal is detected by detecting the frequency variation of the carrier wave, there is provided an abnormal condition detector which compares the lengths of contiguous or closely adjacent periods, or functions thereof, of the received carrier wave.

BACKGROUND OF THE INVENTION

This invention relates to apparatus for protecting an electric powersystem wherein a remote electric quantity is reproduced by transmittinga frequency modulated carrier wave and the reproduced signal is used toprotect the electric power system, and more particularly to apparatusfor detecting and processing an abnormal condition of the transmittedsignal.

To aid understanding of the invention a protective relaying system towhich the invention is applicable will firstly be described withreference to FIG. 1 of the accompanying drawing. In the system shown inFIG. 1, for the purpose of protecting a transmission line TL between twospaced electric power stations or systems A and B, the secondary currentof a current transformer CT associated with the transmission line TL isapplied to a relay unit including a transmitting unit and a receivingunit. The level of the secondary current is converted in the relay unitand then sent to the other electric station after being subjected to afrequency modulation in the transmitting unit. Similarly, the frequencymodulated signal from the other power station is received by thereceiving unit of one station anddemodulated. The demodulated signal andthe signal in one station are used to operate the relay unit, forcausing it to act as a differential relay or a phase comparison relay,for example.

In such a relaying system it is necessary to correctly detect theabnormal conditions of the transmitted signals in order to preventmisoperation of the relaying system caused by the abnormal conditions.To this end, a frequency range supervising system has been used. Moreparticularly, in the frequency modulation transmission system as thecarrier frequency F_(o) is varied by ± ΔF the frequency of the receivedwave is in a range of from F_(o) - ΔF to F_(o) + ΔF. In this case, thefrequency of the received wave is supervised to determine that signalshaving frequencies outside of this range are abnormal signals. However,the detection efficiency of this system is low. Even when the frequencyis varied due to a noise, so long as the received frequency is includedin this range any abnormal condition could not be detected. However, thedemodulated waves are often abnormal. A remarkable example of this caseis shown in FIG. 2 in which FIG. 2a shows a transmitted wave and FIG. 2ba received wave. In both FIGS. 2a and 2b the transmission delay time isomitted. In this example, F_(o) = 1,800 Hz, and ΔF = 600 Hz so that thenormal frequency range is from 1,200 to 2,400 Hz. FIG. 2a shows aportion of a transmitted wave having a frequency of 1,200 Hz while FIG.2b shows a corresponding portion of the received wave but the waveformof a portion near zero point is disturbed due to a noise and has afrequency of 2,400 Hz. By the frequency range supervising system, it isimpossible to detect an abnormal condition, yet the received signal isabnormal because its waveform is greatly disturbed by the noise.Excluding such an extreme case, there are many cases in which even thevariations in the normal frequency range cannot be neglected. FIGS. 3aand 3b show one example of such a case wherein the zero point of asignal having a frequency of 1,800 Hz (FIG. 3a) has been shifted by thenoise so that the frequency of one period has decreased to 1,500 Hzwhereas that of the next period has increased to 2,250 Hz as shown inFIG. 3b. In this case too, the abnormal condition is not detected yet anadverse effect would cause the same trouble as in the case shown in FIG.2.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a novelapparatus for accurately detecting an abnormal condition of atransmitted signal.

Another object of this invention is to provide a novel protectiverelaying system wherein the operation of the relaying apparatus iscontrolled by the output from the abnormal condition detectingapparatus.

According to one aspect of this invention there is provided apparatusfor detecting an abnormal condition of a transmitted signal of the classwherein a carrier wave frequency modulated by an electric quantity istransmitted to a receiving station and the frequency variation of thecarrier wave is detected by an abnormal condition detector installed inthe receiving station so as to detect an abnormal condition of thetransmitted signal, characterized in that the abnormal conditiondetector comprises means for comparing the lengths of contiguous orclosely adjacent periods of the received carrier wave.

According to another aspect of this invention there is provided aprotective relaying system of a transmission line interconnecting firstand second electric stations of the type wherein a carrier wavefrequency modulated by an electric quantity of the first station istransmitted to the second electric station for operating a relayinstalled therein, characterized in that an abnormal condition detectoris provided in the second station, that the detector comprises means forcomparing the lengths of contiguous or closely adjacent periods of thereceived carrier wave, and means responsive to the output of thecomparing means for controlling the relay.

Instead of directly comparing adjacent two periods of the receivedcarrier wave, two average periods in adjacent sections of the receivedcarrier wave or functions of such average periods may be compared. Thus,the abnormal condition detector may be constructed to establish arelation F₁ (T₁) < T₂ or T₂ < F₂ (T₁) or F₁ (T₁) < T₂ < F₂ (T₁) fordetermining a permissible range of the frequency variation of thecarrier wave, where T₁ represents an average period of any section ofthe received carrier wave, T₂ an average period of a section contiguousto or close to said section and F₁ (T₁) and F₂ (T₁) are functions of theaverage period T₁.

Detection of the abnormal condition can be made by using analogue ordigital circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the invention can be more fullyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is a connection diagram showing a carrier wave protectiverelaying system to which the invention is applicable.

FIGS. 2a and 2b and FIGS. 3a and 3b are waveforms showing certaindefects of the prior art abnormal condition detecting apparatus utilizedin the protective relaying system;

FIG. 4 is a block diagram showing one embodiment of the abnormalcondition detecting apparatus embodying the invention;

FIG. 5 is a block diagram showing one example of the construction of thelogical judging circuit LG shown in FIG. 4;

FIG. 6 shows waveforms useful to explain the operation of the apparatusshown in FIGS. 4 and 5;

FIG. 7 is a connection diagram showing a modified abnormal conditiondetecting unit;

FIG. 8 shows waveforms of a frequency division circuit slightly modifiedfrom that shown in FIG. 4;

FIG. 9 shows an abnormal condition detecting unit slightly modified fromthat shown in FIG. 4;

FIG. 10 shows a logical judging circuit modified from that shown in FIG.5;

FIG. 11 shows another example of the abnormal condition detecting unit;

FIG. 12 shows a still further modification of the abnormal conditiondetecting unit;

FIG. 13 shows a diagram for explaining the operation of the abnormalcondition detecting unit shown in FIG. 12;

FIGS. 14, 15 and 16 are graphs showing a permissible period range;

FIG. 17 is a block diagram showing a modification of the circuit shownin FIG. 12;

FIGS. 18 and 19 are graphs showing the permissible period rangecharacteristics of the modified embodiment shown in FIG. 17;

FIG. 20 is a block diagram showing still another embodiment of thisinvention which utilizes an analogue circuit;

FIG. 21 shows waveforms useful to explain the operation of theembodiment shown in FIG. 20;

FIG. 22 is a block diagram showing another embodiment of this invention;

FIG. 23 shows waveforms utilized to explain the operation of theembodiment shown in FIG. 22.

FIG. 24 shows a modified logical judging circuit and FIG. 25 a modifiedup-down counter which are to be substituted in the circuit shown in FIG.11 for detecting only the lower limit of the frequency;

FIG. 26 shows waveforms useful to explain the operation of the circuitshown in FIG. 11 when it is modified by the circuits shown in FIGS. 24and 25;

FIGS. 27 and 28 show modifications of FIGS. 24 and 25, respectively,which are to be substituted in the circuit shown in FIG. 11 fordetecting only the upper limit of the frequency, and

FIG. 29 shows waveforms useful to explain the operation of the circuitshown in FIG. 11 when the circuits shown in FIGS. 27 and 28 aresubstituted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The carrier wave relaying system shown in FIG. 4 comprises a sendingunit SD, a receiving unit RC and a relay unit RY which are identical tothose shown in FIG. 1. An incoming signal I from the transmission lineTL is converted into a signal having a proper level and a limitedbandwith by a filter SF in the sending unit SD and the signal is thensent to the other or receiving end through a voltage-frequency converterVF. In the receiving end, waveform of the carrier signal RW is shaped bya shaping circuit S₁ in the receiving unit RC and its output RT isdemodulated by a frequency-voltage converter FV. The output from thefrequency-voltage converter FV is applied to the relay unit RY foroperating the same. It should be understood that shaping circuit S₁ isprovided with an ordinary filter normally required in the art.

An abnormal conditon detecting unit DET embodying the invention isconnected to the output of shaping circuit S₁. It comprises a frequencydividing circuit S₂ which decreases the frequency of the output signalto one half thus producing outputs Q and Q. The abnormal conditiondetecting unit DET further comprises a multivibrator MV which generatesa clock signal CK, two logical product circuits A₁ and A₂ and an up-downcounter CTR which counts up or performs an addition operation inresponse to the output C₁ from the logical product circuit A₁ and countsdown or performs a subtraction operation in response to the output C₂from the logical product circuit A₂. Since these circuit elements arewell known in the art their detailed description is believedunnecessary. There is also provided a timing signal generating circuitTG which in response to the first pulse of signal C₁ produces a signalC₃ which is applied to the up-down counter CTR for initially setting thesame in a manner to be described later. Signal C₃ is also applied to alogical judging circuit LG which is constructed to judge the output fromthe up-down counter immediately preceding signal C₃ for producing anoutput signal LP which is applied to the relay unit RY, thus controllingthe operation thereof.

FIG. 5 shows one example of the logical judging circuit LG comprisinglogical product circuits A₃ and A₄, a logical sum circuit OR₁, anegation gate circuit N₁, and a JK-flip-flop circuit FF. For the sake ofdescription it is assumed now that the counter CTR shown in FIG. 4 is afour bit binary counter and that outputs B₄ and B₃ of the significanttwo bits thereof and the inversion of B₄ and B₃ of B₄ and B₃ are appliedto the logical product circuit A₃ and A₄, respectively.

The outputs from the logical product circuits A₃ and A₄ are applied tothe K terminal of the flip-flop circuit FF via the logical sum circuitOR₁. The output from the logical sum circuit OR₁ is inverted by negationgate circuit N₁ and is then applied to the J terminal of the flip-flopterminal FF, the clock input circuit CP thereof being connected toreceive signal C₃. As is well known in the art, the output from theflip-flop circuit is determined by the inputs to the J and K terminalsimmediately prior to the input to terminal CP. These operations will bedescribed later together with the operation of the entire system.

The relaying system described above operates as follows. Table I belowand the waveforms shown in FIG. 6 are useful to explain the operation ofthe abnormal condition detecting unit DET shown in FIG. 4. In FIG. 6,symbols RW and CK have the meanings described above, C₁ represents thelogical product of Q and CK, and C₂ the logical product of Q and CK.Accordingly the up-down counter CTR counts up during the interval of Qbut counts down during the interval of Q. When the up-down counter CTRcomprises a four bit binary counter, then it has 16 outputs 0, 1, 2 . .. 15 as shown in Table I.

                  Table I                                                         ______________________________________                                        Count of                                                                      counter                                                                       (C.sub.1 +C.sub.2)                                                                     B.sub.4                                                                              B.sub.3                                                                              B.sub.2                                                                            B.sub.1                                                                            B.sub.4                                                                            B.sub.3                                                                            K    J                             ______________________________________                                         0       0      0      0    0    1    1    1    0                              1(or -15)                                                                             0      0      0    1    1    1    1    0                              2       0      0      1    0    1    1    1    0                              3       0      0      1    1    1    1    1    0                              4       0      1      0    0    1    0    0    1                              5       0      1      0    1    1    0    0    1                              6       0      1      1    0    1    0    0    1                              7       0      1      1    1    1    0    0    1                              8       1      0      0    0    0    1    0    1                              9       1      0      0    1    0    1    0    1                             10       1      0      1    0    0    1    0    1                             11(or -5)                                                                              1      0      1    1    0    1    0    1                             12(or -4)                                                                              1      1      0    0    0    0    1    0                             13(or -3)                                                                              1      1      0    1    0    0    1    0                             14(or -2)                                                                              1      1      1    0    0    0    1    0                             15(or -1)                                                                              1      1      1    1    0    0    1    0                             ______________________________________                                    

Assume now that the counter CTR is initially set to state 1 by signalC₃, then the counter assumes state 2 in response to second signal C₁. Inthis manner, the counter successively counts up, and counts down inresponse to signals C₂. The output of the counter CTR for the last pulseof signal C₂, that is the output immediately prior to signal C₃represents the difference between the numbers of pulses of signals C₁and C₂, in other words, the difference between the widths of Q and Qsucceeding thereto. These relationships will be described with referenceto four sections of No. 1 to No. 4 of the carrier wave RW shown in FIG.6.

In section No. 1, both signals C₁ and C₂ comprises 6 pulses so thatimmediately prior to signal C₃, the content of the counter CTR is just 0and B₃ = B₄ = 0. Accordingly, the output from the logical productcircuit A₄ is "1" so that input to the K and J terminals of theflip-flop circuit FF are respectively "0". Under such steering inputs toterminals J and K, the flip-flop circuit FF is reset to produce an "0"output LP. Or if output LP has been at "0" state, this state will bemaintained, since the JK-flip-flop circuit is constructed to operate inthis manner.

In section No. 2, signals C₁ and C₂ comprise 9 and 5 pulses respectivelyso that the count of the counter CTR immediately prior to signal C₃ is4, that is B₁ = B₂ = B₄ = "0", and B₃ = "1". Accordingly, the outputs ofboth logical product circuits A₃ and A₄ shown in FIG. 5 are 0 and inputsto the K and J terminals are "0" and "1" respectively. Thus, when signalC₃ is applied, the flip-flop circuit sets and the output LP becomes "1".

In section No. 3 signals C₁ and C₂ comprise 5 and 10 pulsesrespectively, and the count of the counter CTR immediately prior tosignal C₃ is -5 so that B₁ = B₂ = B₄ = "1", and B₃ = "0" as in the caseof count +11. In this case too since J = "1" and K = "0", the flip-flopcircuit FF continues its set state even when it receives signal C₃.

In section No. 4 signals C₁ and C₂ comprise 5 and 6 pulses respectivelyso that the count of the counter CTR immediately prior to signal C₃ is-1 and B₁ = B₂ = B₃ = B₄ = "1", J = "0" and K = "1". Accordingly, uponarrival of signal C₃, the flip-flop circuit FF resets to produce anoutput LP = "0".

As above described, in this example, the flip-flop circuit FF producesan output "1" when the number of pulses of signal C₁ is larger than thatof signal C₂ by 4 or the number of pulses of signal C₂ is larger thanthat of signal C₁ by 5. In other words, the periods of the receivedcarrier wave in adjacent sections are compared to each other, and whenthe difference is larger than a prescribed value, it is judged thatthere is an abnormal condition in the received signal and the output LPis produced. In response to output LP, the relay unit RY is controlledin various manners. For example, while the output LP is being produced,the output of the relay unit may be interrupted, or an off delay timermay be interposed between the logical judging circuit LG and the relayunit RY for increasing the interval of output LP. Alternatively, thesensitivity of the relay unit RY may be decreased during the interval ofoutput LP or the judging time of the logical judging circuit may beelongated.

In this example, when the number of pulses of signal C₁ is larger thanthat of signal C₂ by 4 to 11 or when the number of pulses of signal C₂is larger than that of signal C₁ by 5 to 12, the abnormal detectingapparatus is effective, but if the difference of the pulses exceeds saidranges, it can not detect the abnormal condition. For example, whensignals C₁ and C₂ comprise 15 and 3 pulses respectively, the count ofthe counter is 12 and B₁ = B₂ = "0", and B₃ = B₄ = "1" whereby thecondition is judged normal. However, when a sufficient number of bits isused for the counter the limit described above can be extended. Forexample, when a 8 bit counter is used it can count pulses of up to 255which is sufficient for ordinary applications.

The abnormal condition detecting apparatus of this invention isextremely beneficial to protective relaying systems of the type shown inFIG. 1. The detecting apparatus does not operate while the signalstransmitted between power stations are normal but detects abnormalsignals at high speeds and with high sensitivities.

More particularly, when the transmitted signal is normal, since thesteep waveform of the signal input to the voltage-frequency converter VFis alleviated by filter SF the frequency of the transmitted wave doesnot vary rapidly. For example, when the input current I has a frequencyof 60 Hz, and carrier frequency F_(o) = 1,800 Hz, the width of thefrequency shift Δ F = 600 Hz, so that under the steady state thefrequency varies in a range of from 1,200 Hz to 2,400 Hz, and the periodvaries in a range of from 0.83 ms to 0.42 ms, but the maximum differencein the periods of adjacent wave sections is about 0.06 ms. Even when thebuild-up portion and distortion of a fault current are taken intoconsideration it is possible to limit the variation in the frequency orperiod below values less than the values described above.

Although, in practice, a certain allowance is necessary so that whenevervalues exceeding above described normal values appear, the apparatus canimmediately judge at a high speed and high sensitivity that there is anabnormal condition in the transmitted signal.

As has been pointed out before, the apparatus of this invention candetect, at the latest, the abnormal condition in a period succeeding tothe period in which the abnormal condition has occurred, so that itsresponse speed is much faster than that of the prior art apparatus.

It will be clear that the invention is by no means limited to thespecific embodiment described above and that many modifications may bemade within the scope of the invention, as will be seen from thefollowing examples.

I. Variation in the periods to be compared.

Although in the circuit shown in FIG. 4, the frequency divider S₂ wasused to switch between counting up and counting down at each period ofthe carrier wave, where it is desired to demodulate at each one halfperiod a negation circuit N is substituted for the frequency divider S₂,as shown in FIG. 7 for comparing the positive and negative periodsthereby further increasing the speed. In this case, the apparatus canoperate as desired when the counting up is performed in the period inwhich the output RT from the shaping circuit S₁ is "1" and when thecounting down is performed in the period in which RT = "1".

Alternatively, it is possible to compare the widths of adjacent n/2periods (where n is an integer) by slightly changing the construction ofthe frequency divider S₂. This modification is effective where thecarrier frequency is sufficiently higher than the frequency of the inputcurrent so that the system is insensible to disturbances of about oneperiod and can avoid undue detection. FIG. 8 shows the waveforms ofsignals RT, Q and Q when n = 5.

II. Change of the clock pulse frequency.

In FIG. 6, for the sake of clarity, signals Q and Q and clock pulses CKwere depicted such that the build up or build down portions of signals Qand Q and the clock pulse CK are not produced at the same time. Evenwhen they are produced simultaneously the problem caused by it can bereadily solved by increasing the resolution by increasing the clockpulse frequency.

Alternatively, a circuit shown in FIG. 9 can be used. Thus themultivibrator MV, and logical product circuits A₁ and A₂ shown in FIG. 4are substituted by multivibrator MV₁ and MV₂ which are constructed togenerate signals C₁ and C₂ respectively in synchronism with signals Qand Q. Signals C₁ and C₂ are used in the same manner as those shown inFIG. 4.

III. Modification of the logical judging circuit LG.

Although in the example shown in FIG. 4 the abnormal condition detectingapparatus operates when the number of pulses of signal C₁ is larger thanthat of signal C₂ by 4 or more and when the number of the pulses ofsignal C₂ is larger than that of signal C₁ by 5 or more, that is adifference of 1 pulse, this can be improved by increasing the resolutionof the apparatus. In other words, by increasing the limit of judgementby selecting a proper number of the clock pulse frequency suchdifference of one pulse can be neglected. This difference can also beeliminated by slightly modifying the circuit shown in FIG. 5. FIG. 10shows one example of such modification in which the output from alogical product negation circuit NA₁ responding to signals B₁ and B₂ ofthe lower digits of the counter is applied to an additional input of anAND gate circuit A₃. As shown in the following Table II, when the countof the counter is equal to from -1 to -3, the output of the AND gatecircuit A₃ is "1" and when the count is equal to from 0 to +3, theoutput of AND gate circuit A₄ becomes "1", thus attaining the desiredobject.

                  Table II.                                                       ______________________________________                                        Count of                     NA.sub.1                                                                            A.sub.3                                                                             A.sub.4                                                                             CR.sub.1                       counter  B.sub.4                                                                             B.sub.3                                                                             B.sub.2                                                                           B.sub.1                                                                           output                                                                              output                                                                              output                                                                              output                         ______________________________________                                        +5       0     1     0   1   1     0     0     0                              4        0     1     0   0   0     0     0     0                              3        0     0     1   1   1     0     1     1                              2        0     0     1   0   1     0     1     1                              1        0     0     0   1   1     0     1     1                              0        0     0     0   0   0     0     1     1                              -1       1     1     1   1   1     1     0     1                              -2       1     1     1   0   1     1     0     1                              -3       1     1     0   1   1     1     0     1                              -4       1     1     0   0   0     0     0     0                              -5       1     0     1   1   1     0     0     0                              ______________________________________                                    

In this manner, it is possible to obtain any desired limit value of thefrequency by using logic circuits having relatively simple construction.Since such modification is obvious to one skilled in the art, the detailthereof is omitted.

IV Duplication of the detecting unit

While in the circuit shown in FIG. 4 two periods of the carrier wavewere compared for making one judgement at every two periods, it is alsopossible to use two up-down counters for judging alternately. Moreparticularly, one counter is used to count up in response to signal Qand count down in response to signal Q and the other counter is used tocount up in response to signal Q and to count down in response to signalQ. With this modified arrangement it becomes possible to judge in eachperiod by comparing a period with a preceding period, thus increasingthe detection speed.

FIG. 11 shows one example of such modified arrangement. Thus, to theabnormal condition detecting unit DET shown in FIG. 4, are added asecond up-down counter CTR₂, second timing signal generator TG₂ and asecond logical judging circuit LG₂ which are identical to correspondingelements CTR, TG and LG shown in FIG. 4 except that they are connectedto receive signal C₂ from the logical product circuit A₂. A logical sumcircuit OR₂ is provided for producing an output corresponding to thelogical sum of the outputs from two logical judging circuits LG and LG₂.

IV Supervision of the frequency range

It is possible to detect the frequency range by adding certain elementsto the circuit shown in FIG. 4. FIG. 12 shows one example of suchmodification and FIG. 13 shows waveforms of the signals. A timing signalgenerator TGA corresponds to the timing signal generator TG shown inFIG. 4 with one additional input C₂ and one additional output C₄ whichis applied to a logical judging circuit LGA. Signal C₄ corresponds tothe first pulse of signal C₂ as shown in FIG. 13. The logical judgingcircuit LGA is similar to the logical judging circuit LG shown in FIG. 4but having certain additional functions. More particularly, in thecircuit shown in FIG. 4, the logical judging circuit LG determines thedifference between the numbers of pulses of signals C₁ and C₂ inresponse to signal C₃ immediately succeeding these signals whereas inthe circuit shown in FIG. 12 signal C₄ is also applied to the logicaljudging circuit LGA so that it judges the output from the counter CTR,that is the number of pulses of signal C₁ immediately preceeding signalC₄. Although not shown, by using a logical circuit similar to that shownin FIG. 4 it is possible to check the upper and lower limits of thefrequency, thereby supervising the frequency range.

This characteristic is shown by the graph shown in FIG. 14 in which theabscissa represents the output of the counter CTR immediately precedingsignal C₄, that is the first period T₁ and the ordinate represents theoutput from the counter CTR immediately preceding signal C₃, that is thedifference (T₁ - T₂) between the first and second periods T₁ and T₂.Thus, the graph shows a permissible period range, and on the outside ofthe range the logical judging circuit LGA shown in FIG. 12 produces anoutput LP. FIG. 15 is a modified graph in which the ordinate of FIG. 14is changed to period T₂.

Where the feature shown in FIG. 12 is incorporated into the circuitshown in FIG. 11, the upper and lower limits are imposed upon the periodT₂ so that a permissible period range as shown in FIG. 16 can beobtained showing that the supervision of the period range becomes morevigorous.

VI. Supervision of ratio differential action

It is also possible to modify the circuit shown in FIG. 12 such that thelimit of detecting the difference judged by signal C₃ can be variedautomatically in accordance with the number of signals C₁ counted bysignal C₄. Under a normal condition, since the difference betweenadjacent periods appears in proportion to the period the sensitivity ofthe detection can be improved by establishing a limit of detectioncorresponding to the difference. FIG. 17 is a block diagram showing thismodification and FIGS. 18 and 19 are graphs showing the permissibleperiod characteristics. The circuit shown in FIG. 17 comprises aregister RG in addition to the circuit elements shown in FIG. 12. Theregister RG is connected between the timing signal generator TGA and alogical judging circuit LGB. Thus, in response to signal C₄ from thetiming pulse generator LGB, the register RG stores the output of theup-down counter CTR at that time, that is a period T₁. Similar to thelogical judging circuit LGA shown in FIG. 12 the logical judging circuitLGB judges the output from counter CTR at the time of signal C₃ or thedifference T₂ - T₁, but it varies its permissible value according to thecontent stored in the register RG in a manner as shown in FIG. 18. Whenthe ordinate T₁ - T₂ of FIG. 18 is changed to T₂, a graph shown in FIG.19 is obtained.

The characteristic shown in FIG. 18 can readily be obtained by using awell known logical circuit. The inclined portion of the graph can bemade to vary continuously or stepwisely, the slope and the steps beingalso variable. The circuit shown in FIG. 17 gives a permissible periodcharacteristic expressed by a relation F₁ (T₂)<T₂ <F₂ (T₁) whichproduces an output LP whenever the frequency is on the outside of thepermissible range where F₁ (T₁) and F₂ (T₁) show functions of the periodT₁. More particularly, this characteristic means that the permissibleminimum value is determined by the function F₁ (T₁) or T₁, that thepermissible maximum value is determined by the function F₂ (T₁) or T₁and that an abnormal condition is detected when T₂ is on the outside ofthe range. Although in the foregoing embodiments, the minimum andmaximum limits can readily be detected, even if only one of the limitswere detected, the object of this invention could also be attained asdescribed hereunder.

Where only the minimum limit is to be detected, that is where T₂ >F₁(T₁) is made to be the permissible range so that a case wherein theperiod does not satisfy this condition is judged as an abnormalcondition, each of the logical judging circuits LG and LG₂ shown in FIG.11 is changed to a logical judging circuit LG shown in FIG. 24 and alogical sum circuit OR₂ and a logical product circuit A₈ are added tothe input of each of the up-down counters CTR and CTR₂ as shown in FIG.25. In this example it is assumed that the counters are of the 5 bitbinary type. However, as mentioned hereinabove, the resolution of theapparatus is improved by increasing the number of the bits of thecounter. The operation of the circuit shown in FIG. 24 is shown in TableIII.

                  Table III                                                       ______________________________________                                        Count of                                                                      counter B.sub.5                                                                             B.sub.4                                                                              B.sub.3                                                                           B.sub.2                                                                            B.sub.1                                                                           B.sub.5                                                                            B.sub.4                                                                           B.sub.3                                                                            K   J                         ______________________________________                                        16      1     0      0   0    0   0    1   1    0   1                         15      0     1      1   1    1   1    0   0    0   1                         11      0     1      0   1    1   1    0   1    0   1                         10      0     1      0   1    0   1    0   1    0   1                         5       0     0      1   0    1   1    1   0    0   1                         4       0     0      1   0    0   1    1   0    0   1                         3       0     0      0   1    1   1    1   1    1   0                         2       0     0      0   1    0   1    1   1    1   0                         1       0     0      0   0    1   1    1   1    1   0                         0       0     0      0   0    0   1    1   1    1   0                         ______________________________________                                    

Different from Table I, Table III does not show the negative range. Thisis caused by the construction shown in FIG. 25. More particularly,although the up-down counter CTR firstly counts up and then counts down,the logical sum circuit OR₃ and the logical product circuit A₈ preventthe counter from advancing into the negative area from the counting downoperation beyond the counting up operation, since when all of the countsof digits B₁ to B₅ become 0, the logical sum circuit OR₃ produces an "0"output and the logical product circuit A₈ prevents to continue thecounting down operation. In the same manner, the counter CTR₂ counts upaccording to signal C₂ and then counts down according to signal C₂ butprevented from going into negative counts by the logical sum circuit OR₃and the logical product circuit A₈.

FIG. 26 shows waveforms useful to explain the operation of thismodification in which TW shows the waveform of a transmitted signal andRW received waveform whose transmission delay time is omitted. For thesake of description, each period of TW is shown to have a width of 8clock pulses. Due to a disturbance during transmission in the latterhalf of section No.1 the width of the period of the received wave isshown to correspond to 13 clock pulses whereas in the latter half ofsection No.2 the width of the period has changed to 3 clock pulses.

In the previous embodiment, the count of the counter at the end ofsection No.1 was 8-13 = -5 thus detecting an abnormal condition but inthis modification, the count of the counter at the end of section No.1is 0 so that no abnormal condition is detected at this point. The countof the counter CTR at the end of section No.2 is 13-3 = 10, so that theinput at the J terminal of the flip-flop circuit is "1" thus detectingthe abnormal condition, as shown in Table III.

As can be noted from the waveforms shown in FIG. 26, in thismodification constructed to detect only the minimum limit, even when anabnormal condition occurs in the opposite direction, that is when theabnormal condition occurs in a direction to increase the interval of theperiod it is possible to detect the abnormal condition by permitting adelay of only about one period. When an abnormal condition occurs in adirection to increase the interval of the period, such abnormalcondition can be detected without delay in the same manner as theprevious embodiment.

FIGS. 27 and 28 show modifications of FIGS. 24 and 25 respectively fordetecting an abnormal condition in a direction to increase the intervalof the period, that is the permissible range is expressed by a relationT₂ <F₂ (T₁) and whenever the frequency does not satisfy this relationthe abnormal condition is detected. Of course, the circuit shown in FIG.27 is substituted for the logical judging circuits LG and LG₂ shown inFIG. 11 and the circuit shown in FIG. 28 is substituted for the countersCTR and CTR₂ shown in FIG. 11.

The operation of the circuit shown in FIG. 27 is shown in the followingTable IV.

                  Table IV                                                        ______________________________________                                        Count of                                                                      counter  B.sub.5                                                                              B.sub.4                                                                              B.sub.3                                                                            B.sub.2                                                                            B.sub.1                                                                            B.sub.5                                                                            K    J                             ______________________________________                                        6        0      0      1    1    0    1    1    0                             5        0      0      1    0    1    1    1    0                             4        0      0      1    0    0    1    1    0                             3        0      0      0    1    1    1    1    0                             2        0      0      0    1    0    1    1    0                             1        0      0      0    0    1    1    1    0                             0        0      0      0    0    0    1    1    0                             -1       1      1      1    1    1    0    1    0                             -2       1      1      1    1    0    0    1    0                             -3       1      1      1    0    1    0    1    0                             -4       1      1      1    0    0    0    1    0                             -5       1      1      0    1    1    0    0    1                             -6       1      1      0    1    0    1    0    1                             -9       1      0      1    1    1    0    0    1                             -10      1      0      1    1    0    0    0    1                             ______________________________________                                    

In FIG. 28 the counter CTR is shown as a 5 bit binary counter. In thismodification when a signal as shown by RW in FIG. 26 is received thecount of counter CTR at the end of section No.1 is 8-13 = -5 so that an"1" signal is applied to terminal J of the flip-flop circuit whereby theabnormal condition is immediately detected.

FIG. 29 shows waveforms wherein the abnormal condition occurs in adirection to decrease the width of the period of the received wave RW,that is in the direction opposite to that just described. In FIG. 29, itis assumed that the width of one period of the transmitted wave TWcorresponds to 8 pulses or counts as in FIG. 26. The example shown inFIG. 29 shows that in the latter half of No.1 section with width of theperiod of the received wave has decreased to 3 pulses and that in thelatter half of No.2 section the width of one period has increased to 13pulses. In this case, the count of counter CTR at the end of No.1section is 8-3 = 5 and as can be noted from Table IV, J = "0" at thistime so that no abnormal condition is detected. On the other hand, thecount of the counter CTR₂, at the end of No.2 section is 3-13 = -10 andJ = " 1" thus detecting the abnormal condition.

As above described this modification too can attain the object of thisinvention where a delay of one period is permissible.

VII Analogue judging circuit

In all embodiments described above, digital circuits were used but itwill be clearly understood that the object of this invention can also beattained by using analogue circuits.

FIG. 20 shows a block diagram showing still another modification of thisinvention utilizing an analogue circuit as the abnormal conditiondetecting unit and FIG. 21 shows waveforms to explain the operation ofthe circuit shown in FIG. 20. The circuit shown in FIG. 20 comprises anintegrator ITG, a one-shot multivibrator OS and a comparator CMP whichare connected as shown. QA shows a shaped wave of the carrier wavecorresponding to the signal Q shown in FIG. 4 and swinging in thepositive and negative directions about the zero line during alternateperiods of the received carrier wave as shown in FIG. 21. DS and IS showa judging pulse and an initial point setting pulse formed by theone-shot multivibrator OS at the build up portion of the signal QA. Theintegrator ITG integrates the signal QA for producing an output SQAwhich attains a value corresponding to the difference between the widthsof the positive and negative portions of the signal QA at a pointimmediately prior to signal DS. As shown in FIG. 21, during the intervalof signal DS the value of the output SQA is maintained to be judged bythe comparator CMP whether the value is within a predetermined range ornot. If the value is on the outside of the predetermined range, thecomparator CMP produces an output LP. During the interval of signal IS,the integrator is set initially. In other words, as shown by dotted lineportions of the output signal SQA shown in FIG. 21 an initial valueequivalent to that obtained when the integrator begins to integrate fromthe build up portion of signal QA is given to the output signal SQA.These operations are repeated to perform a function similar to the firstembodiment.

VIII Two stage difference or mean value

Although in the foregoing embodiments adjacent periods of the samenumbers were compared, the invention is not limited thereto.

FIG. 22 shows another embodiment of this invention and FIG. 23 showswaveforms useful to explain the operation of this modification. SymbolsQ and Q have the same meaning as in the first embodiment and areproduced by rectifying the received carrier wave. The frequency of thesignal Q is reduced to one half by a second frequency divider S₃ toobtain signals D and D. The frequency of the clock pulse produced bymultivibrator MV is reduced to one half by a third frequency divider S₄to produce a clock pulse CK₁ having a 1/2 frequency. Signals Q, Q, D, D,CK and CK₁ are applied to respective inputs of logical product circuitsA₅, A₆ and A₇. More particularly, the logical product circuit A₅produces an output C₁₁ in response to signals Q and CK₁, the logicalproduct circuit A₆ produces an output C₁₂ in response to signals Q, Dand CK and the logical product circuit A₇ produces an output C₂₂ inresponse to signals D, CK and Q. Binary up-down counters CTR₁ and CTR₂count up in response to signal C₁₁ and count down in response to signalsC₁₂ and C₂₂ respectively. Timing signal generators TG₁ and TG₂ respondto the first pulses of signals C₂₂ and C₁₂ for producing outputs C₁₃ andC₂₃. As before, logical judging circuits LG₁ and LG₂ are provided forjudging the outputs of counters CTR₁ and CTR₂ immediately prior tosignals C₁₃ and C₂₃ for producing outputs respectively which are appliedto a logical sum circuit OR₂ to produce an output LP. Signals C₁₃ andC₂₃ are used to set counters CTR₁ and CTR₂ respectively to their initialor 0 state to prepare for the next counting.

As shown in FIG. 23, the section No. 1 comprises three periods T₁, T₂and T₃ and the circuit shown in FIG. 22 operates to check T₁ -(2·T₂) +T₃. This is because that while during the periods T₁ and T₃, the numberof pulses of signal C₁₁ is counted up and during the period of T₃, thenumber of the pulses of the signal C₁₂ are counted down so that thefrequency of signal C₁₂ is twice that of the signal C₁₁. In the firstembodiment, under the normal condition the maximum difference of thelengths of the periods was above 0.02ms and when the difference exceedsthis value it was determined that there is an abnormal condition. Inaccordance with this embodiment, however, the value of the difference inthe period is from 1 to two times of that of the first embodiment sothat the sensitivity is increased. The equation described above can bemodified as follows.

    T.sub.1 - (2.T.sub.2) + T.sub.3 = (T.sub.1 - T.sub.2) - (T.sub.2 - T.sub.3) (1)

    = (t.sub.1 + t.sub.2 + t.sub.3) - 3t.sub.2                 (2)

    = 3{(t.sub.1 + t.sub.2 + t.sub.3)/3 - t.sub.2 }            (3)

equation (1) represents the difference between the differences of twoadjacent periods, that is, the two stage difference, whereas equations(2) and (3) compare the mean values of two pairs each comprising aplurality of periods. Sections succeeding No. 2 section can be processedin the same manner.

These relationships can be generalized as follows. Taking closelyadjacent first and second periods respectively comprising m/2 periodsand l/2 periods (where m and l are integers), and mean values of thefirst and second periods are compared so as to judge that there is anabnormal condition when the difference exceeds a predetermined value.The term "closely adjacent" is used herein to include various caseswhere two sections are contiguous, one period is included in the other,and two periods are overlapping.

Although various embodiments described above were described inconnection with a protective relaying system for an electric powertransmission line it will be clear that the invention is also applicableto such other systems as an overall backup protective relaying systemfor an electric power system wherein currents, voltages, effectivepowers, wattless powers, etc. of a plurality of stations are transmittedto a central station for overall judgement; a step out protectiverelaying system, and a communication system utilizing frequencymodulation.

Thus, the invention provides a novel apparatus for detecting an abnormalcondition of a transmitted signal and an improved protective relayingsystem utilizing the same which can accurately and promptly detect anabnormal condition of a frequency modulated signal thus avoidingmisoperation as well as overlooking the abnormal condition.

We claim:
 1. In apparatus for detecting an abnormal condition of atransmitted signal of the class wherein a carrier wave frequencymodulated by an electric quantity is transmitted to a receiving stationand the frequency variation of said carrier wave is detected by anabnormal condition detector installed in said receiving station so as todetect an abnormal condition of the transmitted signal, the improvementwherein said abnormal condition detector comprises means for comparingthe length of contiguous or closely adjacent periods of the receivedcarrier wave.
 2. The apparatus according to claim 1 wherein saidabnormal condition detector comprises means for establishing a relationF₁ (T₁)<T₂ for a permissible range of period of said transmitted signaland means responsive to the departure of said period from said range forjudging that there is an abnormal condition of the transmitted signal,where T₁ represents an average period of any section of the receivedcarrier wave, T₂ an average period of a section contiguous to or closeto said section, and F₁ (T₁) represents a function of said averageperiod T₁.
 3. The apparatus according to claim 2 wherein said abnormalcondition detector comprises means for establishing a relation T₂ <F₂(T₁) for the permissible range of the period wherein F₂ (T₁) representsanother function of said average period T₁.
 4. The apparatus accordingto claim 2 wherein said abnormal condition detector comprises means forestablishing a relation F₁ (T₁)<T₂ <F₂ (T₁) for the permissible range ofthe period wherein F₂ (T₁) represents another function of said averageperiod T₁.
 5. The apparatus according to claim 1 wherein said abnormalcondition detector comprises a frequency divider for reducing thefrequency of the received carrier wave to produce positive and negativesignals, a source of clock pulses, a first logical product circuit forproducing the logical product of said positive signal and said clockpulses, a second logical product circuit for producing the logicalproduct of said negative signal and said clock pulses, a up-down counterconnected to receive the outputs of said first and second logicalproduct circuits, a timing signal generator responsive to the outputfrom said first logical product circuit for applying its output to saidup-down counter, and a logical judging circuit responsive to the outputsof said counter and said timing signal generator.
 6. The apparatusaccording to claim 1 wherein said logical judging circuit comprises athird logical product circuit responsive to two adjacent counts of thehigher order digits of said counter, a fourth logical product circuitresponsive to the inversions of said two counts, a logical sum circuitfor producing the sum of said third and fourth logical product circuitsand a flip-flop circuit connected to receive the output from said timingpulse generator, the output from said logical sum circuit and theinvention thereof.
 7. The apparatus according to claim 1 wherein saidabnormal condition detector comprises means for producing signalproportional to the received carrier wave, a negation circuit forinverting said signal, a source of clock pulses, a first logical productcircuit responsive to said signal and said clock pulses, a secondlogical product circuit responsive to the output of said negationcircuit and said clock pulses and a up-down counter connected to respondto the outputs of said first and second logical product circuits.
 8. Theapparatus according to claim 1 wherein said abnormal condition detectorcomprises a frequency divider for reducing the frequency of the receivedcarrier wave to produce positive and negative signals, first and secondmeans respectively responsive to said positive and negative signals forproducing first and second clock pulse signals and a up-down counterconnected to respond to said first and second clock pulse signals. 9.The apparatus according to claim 6 which further comprises a logicalproduct negation circuit responsive to the inversions of two adjacentcounts of the lower order digits of said counter and means for applyingthe output from said logical product negation circuit to an additionalinput of said third logical product circuit.
 10. The apparatus accordingto claim 6 wherein said abnormal condition detector further comprises asecond up-down counter connected in parallel opposition with said firstmentioned up-down counter, a second logical judging circuit, a logicalsum circuit for producing the sum of said two logical judging circuits,and a second timing signal generator responsive to the output of saidlogical product circuit for controlling said second up-down counter. 11.The apparatus according to claim 1 wherein said abnormal conditiondetector comprises a frequency divider for reducing the frequency of thereceived carrier wave to produce positive and negative pulses, a sourceof clock pulses, a first logical product circuit for producing thelogical product of said positive pulses and said clock pulses, a secondlogical product circuit for producing the logical product of saidnegative pulses and said clock pulses, a timing signal generatorresponsive to the outputs of said first and second logical productcircuits for producing two outputs, a up-down counter connected toreceive one of said two outputs together with the outputs from saidfirst and second logical product circuits, and a logical judging circuitconnected to receive said two outputs of said timing signal generatorand the output of said counter.
 12. The apparatus according to claim 11wherein said abnormal condition detector further comprises a registerconnected in the circuit for applying the other output of said timingsignal generator to said logical judging circuit for storing the countsof said counter.
 13. The apparatus according to claim 10 wherein eachlogical judging circuit comprises a third logical product circuit forproducing the logical product of the outputs of three upper digits of acounter and a flip-flop circuit connected to receive the output and theinversion thereof from said third logical product circuit and the outputof a timing signal generator, and wherein each counter is provided witha logical sum circuit which produces the logical sum of the outputs ofall digits of the counter and a logical product circuit for producingthe logical product of the outputs of said second logical productcircuit and said logical sum circuit.
 14. The apparatus according toclaim 10 wherein each logical judging circuit comprises a third logicalproduct circuit for producing the logical product of the counts of uppertwo digits of the counter, a logical sum circuit for producing thelogical sum of the output from said third logical product circuit andthe inverted count of a digit higher than said two digits and aflip-flop circuit connected to receive the output, and the inversionthereof, from said logical sum circuit.
 15. In apparatus for detectingan abnormal condition of a transmitted signal of the class wherein acarrier wave frequency modulated by an electric quantity is transmittedto a receiving station and the frequency variation of the carrier waveis detected by an abnormal condition detector installed in saidreceiving station so as to detect an abnormal condition of thetransmitted signal, the improvement wherein some abnormal conditiondetector comprises means responsive to the received carrier wave foralternately producing positive and negative waves in alternate periodsof the received carrier wave, an integrator for integrating the outputfrom said means, a comparator responsive to the output of saidintegrator for producing the difference between the widths of saidpositive and negative waves, and a one-shot multivibrator responsive tothe output of said means for producing an initial point setting pulseapplied to said integrator and a judging pulse applied to saidintegrator and said comparator.
 16. The apparatus according to claim 1wherein said abnormal condition detector comprises a first frequencydivider for reducing the frequency of the received carrier wave toproduce positive and negative signals, a second frequency dividerresponsive to said positive signal for producing positive and negativerectangular waves, a source of clock pulses, a third frequency dividerfor producing clock pulses of a reduced frequency, a first logicalproduct circuit for producing the logical product of said positivesignal and said clock pulses of the reduced frequency, a second logicalproduct circuit for producing the logical product of said negativesignal, said positive rectangular wave and said clock pulses, a thirdlogical product circuit for producing the logical product of saidnegative rectangular wave, said negative signal and said clock pulse, afirst up-down counter responsive to the outputs from said first andsecond logical product circuits, a first logical judging circuitconnected to receive the output from said first up-down counter, a firsttiming signal generator responsive to the output from said third logicalproduct circuit for producing an output applied to said first up-downcounter and said first logical judging circuit, a second up-down counterresponsive to the outputs from said first and third logical productcircuits, a second timing signal generator responsive to the output fromsaid second logical product circuit for producing an output applied tosaid second up-down counter and said second logical judging circuit, anda logical sum circuit for producing the logical sum of the outputs ofsaid first and second logical judging circuits.
 17. In a protectiverelaying system of a transmission line interconnecting first and secondelectric stations of the type wherein a carrier wave frequency modulatedby an electric quantity of said first station is transmitted to saidsecond electric station for operating a relay installed therein, theimprovement which comprises an abnormal condition detector provided insaid second station and including means for comparing the lengths ofcontiguous or closely adjacent periods of the received carrier wave, andmeans responsive to the output of said comparing means for controllingsaid relay.
 18. In a protective relaying system of a transmission lineinterconnecting first and second electric stations of the type wherein acarrier wave frequency modulated by an electric quantity of said firststation is transmitted to said second electric station for operating arelay installed therein, the improvement which comprises an abnormalcondition detector provided in said second station and including meansresponsive to the received carrier wave for alternately producingpositive and negative waves in alternate periods of the received carrierwave, an integrator for integrating the output from said means, acomparator responsive to the output of said integrator for producing thedifference between the widths of said positive and negative waves, aone-shot multivibrator responsive to the output of said means forproducing an initial point setting pulse applied to said integrator anda judging pulse applied to said integrator and said comparator, andmeans responsive to the output of said comparator for controlling saidrelay.